library IEEE;
use IEEE.std_logic_1164.all;

entity EQUALCHK is
    port (
        A: in STD_LOGIC_VECTOR (0 to 7);
        B: in STD_LOGIC_VECTOR (0 to 7);
        C: in STD_LOGIC_VECTOR (0 to 7);
        AEQB: inout STD_LOGIC;
        BEQC: inout STD_LOGIC;
        AEQC: inout STD_LOGIC;
        ABCEQ: out STD_LOGIC
    );
end EQUALCHK;

architecture EQUALCHK_arch of EQUALCHK is
begin
  AEQB <= '1' when A = B else '0';
  BEQC <= '1' when B = C else '0';
  AEQC <= '1' when A = C else '0';
  ABCEQ <= '1' when (AEQB and BEQC and AEQC)='1' else '0';
end EQUALCHK_arch;