library IEEE;
use IEEE.std_logic_1164.all;

entity INV4 is
  port (X: in STD_LOGIC_VECTOR (0 to 3); Y: out STD_LOGIC_VECTOR (0 to 3) );
end INV4;

architecture INV4_A of INV4 is
begin
  Y <= not X;
end INV4_A;