-- ACTIVE-CAD-2-VHDL, 2.5.5.50, Tue Dec 15 21:54:49 1998

library IEEE;
use IEEE.std_logic_1164.all;

entity INV8 is port (
	I : in STD_LOGIC_VECTOR (7 downto 0);
	O : out STD_LOGIC_VECTOR (7 downto 0)
); end INV8;

architecture SCHEMATIC of INV8 is

--COMPONENTS

component INV port (
	I : in STD_LOGIC;
	O : out STD_LOGIC
); end component;

--SIGNALS



begin

--SIGNAL ASSIGNMENTS


--COMPONENT INSTANCES

X36_1I30 : INV port map(
	I => I(4),
	O => O(4)
);
X36_1I31 : INV port map(
	I => I(5),
	O => O(5)
);
X36_1I32 : INV port map(
	I => I(6),
	O => O(6)
);
X36_1I33 : INV port map(
	I => I(7),
	O => O(7)
);
X36_1I34 : INV port map(
	I => I(3),
	O => O(3)
);
X36_1I35 : INV port map(
	I => I(2),
	O => O(2)
);
X36_1I36 : INV port map(
	I => I(1),
	O => O(1)
);
X36_1I37 : INV port map(
	I => I(0),
	O => O(0)
);

end SCHEMATIC;