library IEEE;
use IEEE.std_logic_1164.all;

entity V3statex is
    port (
        G_L: in STD_LOGIC;                        -- Global output enable
        SEL: in STD_LOGIC_VECTOR (1 downto 0);    -- Input select 0,1,2,3 ==> A,B,C,D
        A, B, C, D: in STD_LOGIC_VECTOR (1 to 8); -- Input buses
        X: out STD_ULOGIC_VECTOR (1 to 8)         -- Output bus (three-state)
    );
end V3statex;

architecture V3states of V3statex is
constant ZZZZZZZZ: STD_ULOGIC_VECTOR := ('Z','Z','Z','Z','Z','Z','Z','Z');
begin
  process (G_L, SEL, A)
  begin
    if G_L='0' and SEL = "00" then X <= To_StdULogicVector(A);
    else X <= ZZZZZZZZ;   
    end if;
  end process;

  process (G_L, SEL, B)
  begin
    if G_L='0' and SEL = "01" then X <= To_StdULogicVector(B);
    else X <= ZZZZZZZZ;   
    end if;
  end process;

  process (G_L, SEL, C)
  begin
    if G_L='0' and SEL = "10" then X <= To_StdULogicVector(C);
    else X <= ZZZZZZZZ;   
    end if;
  end process;

  process (G_L, SEL, D)
  begin
    if G_L='0' and SEL = "11" then X <= To_StdULogicVector(D);
    else X <= ZZZZZZZZ;   
    end if;
  end process;
  
end V3states;