library IEEE;
use IEEE.std_logic_1164.all;

entity V3to8dec is
    port (
        G1: in STD_LOGIC;
        G2: in STD_LOGIC;
        G3: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (2 downto 0);
        Y: out STD_LOGIC_VECTOR (0 to 7)
    );
end V3to8dec;

architecture V3to8dec_b of V3to8dec is
  signal Y_s: STD_LOGIC_VECTOR (0 to 7);  -- internal signal
begin
process(A, G1, G2, G3, Y_s)
  begin
    case A is
      when "000" => Y_s <= "10000000";
      when "001" => Y_s <= "01000000"; 
      when "010" => Y_s <= "00100000"; 
      when "011" => Y_s <= "00010000"; 
      when "100" => Y_s <= "00001000"; 
      when "101" => Y_s <= "00000100"; 
      when "110" => Y_s <= "00000010"; 
      when "111" => Y_s <= "00000001"; 
      when others => Y_s <= "00000000";
    end case;
    if (G1 and G2 and G3)='1' then Y <= Y_s;
    else Y <= "00000000";
    end if;
  end process;
end V3to8dec_b;