library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity V3to8dec is
    port (
        G1: in STD_LOGIC;
        G2: in STD_LOGIC;
        G3: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (2 downto 0);
        Y: out STD_LOGIC_VECTOR (0 to 7)
    );
end V3to8dec;

architecture V3to8decc of V3to8dec is
begin
process (G1, G2, G3, A)
  variable i: INTEGER range 0 to 7;
  begin
    Y <= "00000000";
    if (G1 and G2 and G3) = '1' then
      for i in 0 to 7 loop
        if i=A then Y(i) <= '1'; end if;
      end loop;   
    end if;
  end process;
end V3to8decc;