library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
    port (
        G1: in STD_LOGIC;
        G2A_L: in STD_LOGIC;
        G2B_L: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (2 downto 0);
        Y_L: out STD_LOGIC_VECTOR (0 to 7)
    );
end V74x138;

architecture V74x138_b of V74x138 is
  signal G2A, G2B: STD_LOGIC;             -- active-high version of inputs
  signal Y: STD_LOGIC_VECTOR (0 to 7);    -- active-high version of outputs
  signal Y_s: STD_LOGIC_VECTOR (0 to 7);  -- internal signal
begin
    G2A <= not G2A_L; -- convert inputs
    G2B <= not G2B_L; -- convert inputs
    Y_L <= Y;         -- convert outputs
    with A select Y_s <=
      "10000000" when "000",
      "01000000" when "001",
      "00100000" when "010",
      "00010000" when "011",
      "00001000" when "100",
      "00000100" when "101",
      "00000010" when "110",
      "00000001" when "111",
      "00000000" when others;
    Y <= not Y_s when (G1 and G2A and G2B)='1' else "00000000";
end V74x138_b;