library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
    port (
        G1: in STD_LOGIC;
        G2A_L: in STD_LOGIC;
        G2B_L: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (2 downto 0);
        Y_L: out STD_LOGIC_VECTOR (0 to 7)
    );
end V74x138;

architecture V74x138_c of V74x138 is
  signal G2A, G2B: STD_LOGIC;             -- active-high version of inputs
  signal Y: STD_LOGIC_VECTOR (0 to 7);  -- active-high version of outputs
  component V3to8dec port (G1,G2,G3: in STD_LOGIC;
                           A: in STD_LOGIC_VECTOR (2 downto 0);
                           Y: out STD_LOGIC_VECTOR (0 to 7) ); end component;
begin
  G2A <= not G2A_L;   -- convert inputs
  G2B <= not G2B_L;   -- convert inputs
  Y_L <= not Y;       -- convert outputs
  U1: V3to8dec port map (G1, G2A, G2B, A, Y);
end V74x138_c;