--
--  File: comp8.vhd
--  created by Design Wizard: 12/18/98 16:42:06
--
library IEEE;
use IEEE.std_logic_1164.all;

entity comp8 is
    port (
        X: in STD_LOGIC_VECTOR (7 downto 0);
        Y: in STD_LOGIC_VECTOR (7 downto 0);
        XGTY: out STD_LOGIC;
        XEQY: out STD_LOGIC
    );
end comp8;

architecture comp8d of comp8 is
function VTOI (X: STD_LOGIC_VECTOR) return INTEGER is
  variable RESULT: INTEGER;
begin
  RESULT := 0;
  for i in X'RANGE loop
    RESULT := RESULT * 2;
    case X(i) is
      when '0' | 'L'  => null;
      when '1' | 'H'  => RESULT := RESULT + 1;
      when others     => null;
    end case;
  end loop;
  return RESULT;
end VTOI;
begin
   XGTY <= '1' when VTOI(X) > VTOI(Y) else '0';
   XEQY <= '1' when X = Y else '0';
end comp8d;