library IEEE;
use IEEE.std_logic_1164.all;

entity ADDER2 is
    port ( A, B: in  STD_LOGIC_VECTOR(1 downto 0);
           CI:   in  STD_LOGIC;
           S:    out STD_LOGIC_VECTOR(2 downto 0) );
end ADDER2;

architecture ADDER2_arch of ADDER2 is

component FA port ( A, B, CI: in  STD_LOGIC;
                    S, CO:    out STD_LOGIC );
end component;

signal C: STD_LOGIC_VECTOR(0 to 2);
begin
  C(0) <= CI;
  U1: for i in 0 to 1 generate
    U1C: FA port map (A(i), B(i), C(i), S(i), C(i+1));
  end generate;
  S(2) <= C(2);
end ADDER2_arch;