library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity fixupsel is
    port (
        S:    in UNSIGNED (3 downto 0);          -- Shift amount, 0-15
        FSEL: out STD_LOGIC_VECTOR(15 downto 0)  -- Select output
    );
end fixupsel;

architecture fixupsel_arch of fixupsel is
begin
process(S)
  begin
    for i in 0 to 15 loop
      if i < CONV_INTEGER(S) then FSEL(i) <= '1'; 
      else FSEL(i) <= '0';  end if;
    end loop;
  end process;
end fixupsel_arch;