library IEEE;
use IEEE.std_logic_1164.all;

entity smexamp is 
  port ( CLOCK, A, B: in STD_LOGIC;
         Z: out STD_LOGIC );
end;

architecture smexampa_arch of smexamp is
type Sreg_type is (INIT, LOOKING, OK);
signal Sreg: Sreg_type;
signal lastA: STD_LOGIC;
begin

  process (CLOCK) -- state-machine states and transitions
  begin
    if CLOCK'event and CLOCK = '1' then
      lastA <= A;
      case Sreg is
        when INIT    =>                    Sreg <= LOOKING;
        when LOOKING => if    A=lastA then Sreg <= OK;
                        else               Sreg <= LOOKING;
                        end if;
        when OK      => if    B='1'   then Sreg <= OK;
                        elsif A=lastA then Sreg <= OK;
                        else               Sreg <= LOOKING;
                        end if;
        when others  =>                    Sreg <= INIT;
      end case;
    end if;
  end process;

  with Sreg select  -- output values based on state
    Z <= '1' when OK,
         '0' when others;
         
end smexampa_arch;